1. Field of the Invention
The invention relates to a semiconductor device and, in particular, to a symmetrical inductor in differential operation.
2. Description of the Related Art
Many digital and analog elements and circuits have been successfully applied to semiconductor integrated circuits. Such elements may include passive components, such as resistors, capacitors, or inductors. Typically, a semiconductor integrated circuit includes a silicon substrate. One or more dielectric layers are disposed on the substrate, with one or more metal layers disposed in the dielectric layers. The metal layers may be employed to form on-chip elements, such as on-chip inductors, by current semiconductor technologies.
Conventionally, the on-chip inductor is formed over a semiconductor substrate and employed in integrated circuits designed for radio frequency (RF) band. FIG. 1 is a plan view of a conventional two-turn symmetrical inductor. The inductor is formed in an insulating layer 110 on a substrate 100, comprising a first winding portion and a second winding portion symmetrical with respect to the dashed line 2 on the insulating layer 100. The first winding portion comprises a first semi-circular conductive line 101 and a second semi-circular conductive line 103 and the second winding portion comprises a third semi-circular conductive line 102 and a fourth semi-circular conductive line 104. The second semi-circular conductive line 103 is parallel to and located outside the first semi-circular conductive line 101. The fourth semi-circular conductive line 104 is parallel to and located outside the third semi-circular conductive line 102. Each semi-circular conductive line has a first end 10 and a second end 20, in which the first end 10 of the first semi-circular conductive line 101 extends to connect the first end 10 of the third semi-circular conductive line 102.
To maintain geometric symmetry, the second end 20 of the second semi-circular conductive line 103 is electrically connected to the second end 20 of the third semi-circular conductive line 102 through a lower cross-connection (underpass) 111. Moreover, the second end 20 of the fourth semi-circular conductive line 104 is electrically connected to the second end 20 of the first semi-circular conductive line 101 through an upper cross-connection 113. The first ends 10 of the second and fourth semi-circular conductive lines 103 and 104 have lateral extending portions 30 and 40 for inputting/outputting signals (not shown).
In order to improve the quality factor (i.e. Q value) of the inductor, techniques have been developed to increase the line width of each semi-circular conductive line, as shown in FIG. 2. Elements in FIG. 2 the same as those in FIG. 1 bear the same reference numbers and are not described again.
Currently, wireless communication chip designs frequently use differential circuits to reduce common mode noise, with inductors applied therein symmetrically. In the inductors shown in FIGS. 1 and 2, the lower cross-connection 111 is relatively closer to the substrate 100 with respect to the upper cross-connection 113. Thus, the parasitic capacitance between the substrate 100 and the primary coil constituted by the second semi-circular conductive lines 103, the third semi-circular conductive lines 102 and the lower cross-connection 111 exceeds that between the substrate 100 and the secondary coil constituted by the first semi-circular conductive lines 101, the fourth semi-circular conductive lines 104 and the upper cross-connection 111. Moreover, since the lower cross-connection 111 is thinner than the upper cross-connection 113, the conductor loss of the primary coil also exceeds that of the secondary coil. As a result, such an inductor cannot effectively reduce common mode noise in differential operation.
Thus, there exists a need in the art for an improved symmetrical inductor design to reduce common mode noise.